Two-dimensional semiconductor devices presently in production on a commercial basis include active and passive elements formed on one major surface of a substrate. In this instance, the integration density of the semiconductor elements formed on a single substrate can be increased by reducing the design rules and the sizes of the semiconductor elements. Excessive reduction of the design rules would however raise another problem in the fabrication process of semiconductor devices and would thus invite substantial reduction in the yield in the production of the devices. This means that reduction of the design rules is restricted from both technological and commercial points of view.
A three-dimensional semiconductor device has therefore been proposed with a view to achieving a drastically increased degree of integration density. Some methods are presently available for the fabrication of such a three-dimensional semiconductor device.
One of these prior-art methods is proposed by S. Kawamura and disclosed in International Electron Devices Meeting (IEDM) Technical Digests, 1983, pp. 364. In Kawamura's method, active and passive semiconductor elements are first formed on and/or in a major surface of a substrate and an insulating layer is thereafter deposited on the surface of the substrate to cover the individual semiconductor elements. In the description that follows, the layer which is thus formed on the major surface of a substrate and which contains active and/or passive semiconductor elements formed on and/or in the substrate and electrically isolated from other semiconductor elements will be referred to as functional layer. A polysilicon layer is then deposited on the insulating layer formed on the functional layer and is irradiated with a laser beam or an electron beam or heated by a strip heater so that the polysilicon is crystallized to provide a silicon-on-insulator (SOI) structure. In this crystallized polysilicon layer are then formed active and passive semiconductor elements to form a second functional layer, followed by interlayer wiring between the semiconductor elements in the first and second functional layers. These steps are repeated until a three-dimensional semiconductor device including two or more functional layers electrically isolated from one another results.
Thus, the method of Kawamura is, in essence, such that a plurality of functional layers are stacked one upon another by repeating the step of crystallizing a polysilicon layer, the step of forming semiconductor elements on the crystallized polysilicon layer and the step of covering these semiconductor elements with an insulating layer. Such a method has drawbacks in that difficulties are encountered in parallelizing the process steps and accordingly an objectionably prolonged period of time is required for the fabrication of a three-dimensional semiconductor device. It may also be pointed out that the semiconductor elements which have been formed on the substrate are subjected to heat during the step of crystallizing a polysilicon layer and would cause changes in the design parameters of the elements. Where, furthermore, a defective semiconductor element happens to be produced in any of the functional layers being formed one after another, such a semiconductor element could not be found out pending the post-fabrication inspection. This would also lead to a decrease in the yield of fabrication of a three-dimensional semiconductor device. Another problem is that the prior-art method is not fully acceptable for the production of semiconductor devices on a quantity basis since techniques making it possible to implement SOI structures with sufficient areas are indispensable for this purpose.
Another known method of fabricating a three-dimensional semiconductor device is proposed by R. D. Etchells et al and is described in the article "Development of a three-dimensional circuit integration technology and computer architecture", SPIE, vol. 282, Technical Issues in Focal Plane Development, pp. 64-74, 1981. This article focuses on the techniques of forming "feedthroughs" in each of stacked silicon chips and the techniques of forming "microinterconnects" to carry signals through the silicon chips. The feedthroughs are produced by the deposition of an array of aluminum dots on the surface of a silicon chip followed by the thermomigration of liquid droplets of aluminum through the chip. On the other hand, the formation of the microinterconnects starts with the deposition of a 1 mil thick spacer-bump on the surface of a chip. A thin film of solder alloy connected to a circuit connection is deposited on this spacer bump and thereafter the spacer-bump is etched out to allow the solder alloy film to float as a free-standing structure over the surface of the chip. The solder alloy, or microspring, on one silicon chip extends in crossing relationship to the microspring on the adjacent chip. The stacked silicon chips are then lightly pressed upon to cause the microsprings on the adjacent silicon chips to plastically deform against each other, whereupon the microsprings thus brought into contact with each other between every two of the stacked silicon chips are thermally fused together.
In connection with this prior-art method of fabricating a three-dimensional semiconductor device, there is further an article published by J. Y. M. Lee et al in "Aluminum Thermomigration Technology for 3-Dimensional Integrated Circuits", IEDM Technical Digests, 1983, pp. 66. This article teaches formation of an integrated circuit with CMOS FETs on a wafer which has been formed with feedthroughs by the thermomigration process, followed by formation of aluminum pads on the reverse surface of the wafer. No particulars regarding the geometry, particularly the lengthwise measurements of the microinterconnects are clarified in the article although the feedthroughs are stated to measure 4 mils in diameter. The illustrations appearing in the article according to R. D. Etchells et al however suggest that the lengths of the interconnects are approximately 3.3 times the diameters of the feedthroughs. Such lengths of the interconnects must be required to avoid break of the interconnects when the interconnects are caused to plastically deform distances approximating the 1 mil spacing between the surface of the chip and the interconnects floating over the chip surface. Where such long interconnects are arranged in crossing relationship between the adjacent silicon chips, considerably large proportions of the total areas of the chips are used for the coupling of the interconnects. This imposes restriction on the number of the interconnects available on each chip and results in reduction in the area of the chip available for the formation of semiconductor elements.
It is, accordingly, an important object of the present invention to provide a process of fabricating a three-dimensional semiconductor device with a drastically increased integration density.
It is another important object of the present invention to provide a process of fabricating a three-dimensional semiconductor device which can be manufactured by steps some of which can be parallelized to permit reduction of the time required for the production of the three-dimensional semiconductor device.
It is still another important object of the present invention to provide a process of fabricating a three-dimensional semiconductor device wherein each of the semiconductor elements formed during the process can be inspected for proper functioning at any stage of the process.
It is still another important object of the present invention to provide a process of fabricating a three-dimensional semiconductor device composed of multilayer structural portions resulting from two or more multilayer structures which can be integrally combined together by heating at a relatively low temperature which will not affect the performance characteristics or design parameters of each of the semiconductor elements in the multilayer structures.
It is still another important object of the present invention to provide a process of fabricating a three-dimensional semiconductor device composed of multilayer structural portions resulting from two or more multilayer structures which can be integrally combined together with use of minimum areas of the multilayer structures and without sacrificing the number of the semiconductor elements to be formed in each of the multilayer structures even when an increased number of multilayer structures are to be combined together.
Yet, it is another important object of the present invention to provide a process of fabricating a three-dimensional semiconductor device economically and with a satisfactory fabrication yield.